The present invention is generally directed to a method for providing plugs in via or contact holes in integrated circuit chips and devices. More particularly, the present invention is directed to a method of providing electrical contact between distinct conductive layers in very large scale integrated circuits (VLSI).
One of the most serious problems associated with the manufacture of very large integrated circuits is in providing adequate step coverage for small openings. As circuit dimensions shrink, contact hole sizes must also be reduced. These holes or vias are provided to make contact between different layers of metallization or between other conductive layers in VLSI devices. It is not sufficient to simply cover over a hole, but rather it is necessary that electrically conductive material be deposited so as to fill the hole and make contact with an underlying conductive layer and to extend through the via opening sufficiently far so as to enable contact with an upper conductive layer. These conductive metallization layers are appropriately patterned to achieve electrical interconnections between various components and between various points on a circuit chip. As the opening size is shrunk, however, step coverage at the edge of the openings is more and more difficult particularly for metals such as aluminum which is an otherwise generally desirable constituent of various metallization layers.
One method that is employed to solve step coverage problems is by tapering the contact hole so that less "shadowing" occurs during metal deposition. However, tapering of the vias is not an effective method for reducing contact opening diameter.
Another problem that must be addressed by any interlevel connection method or structure is the fact that in an integrated circuit chip there exists a need for connection through openings of various depths. Since many structures are formed by etching which generally takes place at the same rate across the hole surface of the substrate, structures exhibiting different depth dimensions are affected differently. In particular, the use of tapered holes renders it difficult to control the dimensions for openings of various depths. Accordingly, it is seen that tapering of the via walls is not an entirely adequate solution for the step coverage problem for small interlevel openings.
One of the other methods that has been proposed for the solution of this problem is the lift-off of aluminum. However, the aluminum lift-off process does not work well for very small openings and large complicated circuits.